Spacer structure for double-sided-cooled power module and method of manufacturing the same
A spacer structure, which connects an insulating substrate and a semiconductor chip of a double-sided-cooled power module, includes: a conductive material layer which is composed of a composite material; an underlying plating layer disposed on the conductive material layer; and a copper plating layer disposed on the underlying plating layer, in which the copper plating layer is in contact with a joining material that joins the spacer to the semiconductor chip and the insulating substrate.
1. A spacer structure which connects an insulating substrate and a semiconductor chip of a double-sided-cooled power module, the spacer structure comprising:
a conductive material layer composed of a composite material;
an underlying plating layer disposed on the conductive material layer; and
a copper plating layer disposed on the underlying plating layer,
wherein the copper plating layer is in contact with a joining material that joins the spacer to the semiconductor chip and the insulating substrate.
2. The spacer structure of claim 1 , wherein the underlying plating layer is composed of one metal selected from a group consisting of nickel (Ni), titanium (Ti), chromium (Cr), and cobalt (Co).
3. The spacer structure of claim 1 , wherein the copper plating layer has a thickness of 5 μm or more.
4. The spacer structure of claim 1 , further comprising a metal layer disposed on the copper plating layer.
5. The spacer structure of claim 4 , wherein the metal layer is composed of one metal selected from a group consisting of gold (Au), silver (Ag), and palladium (Pd).
6. A method of manufacturing a spacer which connects an insulating substrate and a semiconductor chip of a double-sided-cooled power module, the method comprising:
applying an underlying plating layer onto a conductive material layer composed of a composite material; and
applying a copper plating layer onto the underlying plating layer,
wherein the copper plating layer is in contact with a joining material that joins the spacer to the semiconductor chip and the insulating substrate.
7. The method of claim 6 , wherein the underlying plating layer is composed of one metal selected from a group consisting of nickel (Ni), titanium (Ti), chromium (Cr), and cobalt (Co).
8. The method of claim 6 , wherein the copper plating layer has a thickness of 5 μm or more.
9. The method of claim 6 , further comprising applying a metal layer onto the copper plating layer.
10. The method of claim 9 , wherein the metal layer is composed of one metal selected from a group consisting of gold (Au), silver (Ag), and palladium (Pd).