Method and system for offline program/erase count estimation
In general, embodiments of the technology relate to a method for characterizing persistent storage. The method includes selecting a sample set of physical addresses in a solid state memory module, where the sample set of physical addresses is associated with a region in the solid state memory module (SSMM). The method further includes issuing a write request to the sample set of physical addresses, after issuing the write request, issuing a request read to the sample set of physical addresses to obtain a copy of the data stored in the sample set of physical addresses, obtaining an error parameter for the copy of the data, determining a calculated P/E cycle value for the SSMM using at least the error parameter; and storing the calculated P/E cycle value in the SSMM.
1. A method for characterizing persistent storage, the method comprising:
selecting a sample set of physical addresses in a solid state memory module (SSMM), wherein the sample set of physical addresses is associated with a region in the SSMM, wherein the selecting is initiated when a P/E cycle value for the SSMM is unknown;
issuing a write request to the sample set of physical addresses;
after issuing the write request, issuing a request read to the sample set of physical addresses to obtain a copy of the data stored in the sample set of physical addresses;
obtaining an error parameter for the copy of the data;
determining a calculated P/E cycle value for the SSMM using at least the error parameter; and
storing the calculated P/E cycle value in the SSMM.
2. The method of claim 1 , further comprising:
after the selecting and prior to issuing the write request:
issuing an erase request to erase all data from the sample set.
3. The method of claim 1 , wherein the error parameter is a failed bit count (FBC).
4. The method of claim 3 , wherein obtaining the error parameter comprises using a known data pattern of the data written to the SSMM in response to the write request.
5. The method of claim 1 , wherein obtaining the error parameter comprises obtaining the error parameter from an error correcting code (ECC) decoder in a storage module controller, wherein the SSMM and the storage module controller are located in a storage module.
6. The method of claim 1 , wherein the error parameter is a decoding latency.
7. The method of claim 1 , wherein the SSMM is one of a plurality of SSMM in a storage module.
8. The method of claim 1 , wherein the SSMM comprises NAND flash.
9. The method of claim 1 , wherein the calculated P/E cycle value is a P/E cycle value range.
10. A non-transitory computer readable medium comprising computer readable program code, which when executed by a computer processor enables the computer processor to:
select a sample set of physical addresses in a solid state memory module (SSMM), wherein the sample set of physical addresses is associated with a region in the SSMM, wherein the selecting is initiated when a P/E cycle value for the SSMM is unknown;
issue a write request to the sample set of physical addresses;
after issuing the write request, issue a request read to the sample set of physical addresses to obtain a copy of the data stored in the sample set of physical addresses;
obtain an error parameter for the copy of the data;
determine a calculated P/E cycle value for the SSMM using at least the error parameter; and
store the calculated P/E cycle value in the SSMM.
11. The non-transitory computer readable medium of claim 10 further comprising computer readable program code, which when executed by the computer processor enables the computer processor to:
after the selecting and prior to issuing the write request:
issue an erase request to erase all data from the sample set.
12. The non-transitory computer readable medium of claim 10 , wherein the error parameter is a failed bit count (FBC).
13. The non-transitory computer readable medium of claim 10 , wherein obtaining the error parameter comprises obtaining the error parameter from an error correcting code (ECC) decoder in a storage module controller, wherein the SSMM and the storage module controller are located in the storage module.
14. The non-transitory computer readable medium of claim 10 , wherein the error parameter is a decoding latency.