Buried metal technique for critical signal nets
Various implementations described herein are related to a device with a frontside power network and a backside power network. The frontside power network may include frontside supply rails coupled to logic circuitry, and also, the backside power network may include buried supply rails. Also, at least one buried supply rail of the buried supply rails may be used as a backside signal path for providing at least one critical signal net to the logic circuitry.
1. A device, comprising:
frontside power network having frontside supply rails coupled to logic circuitry; and
backside power network having buried supply rails;
wherein at least one buried supply rail of the buried supply rails is used as a backside signal path for providing a critical signal net to the logic circuitry.
2. The device of claim 1 , wherein the device has a cell architecture including a standard cell architecture or a custom cell architecture.
3. The device of claim 1 , further comprising:
buried transition vias that couple the at least one buried supply rail to frontside metals,
wherein the buried transition vias couple the at least one buried supply rail to the logic circuitry to thereby provide the critical signal net to the logic circuitry by way of coupling the backside signal path to the frontside metals.
4. The device of claim 1 , wherein:
the frontside supply rails are formed with frontside metal, and
the buried supply rails are formed with backside buried metal.
5. The device of claim 4 , wherein:
the backside signal path is formed with a backside buried metal that provides a buried signal path for the critical signal net, and
the critical signal net refers to an internal clock signal that is timing critical.
6. The device of claim 5 , wherein the internal clock signal refers to a global timing pulse (GTP) that is provided to the logic circuitry.
7. The device of claim 1 , wherein:
the logic circuitry refers to a logic gate that is configured to receive the critical signal net and provide a row clock signal, and
signal routing is provided with the at least one buried supply rail to the logic gate as the backside signal path for providing the critical signal net to the logic gate.
8. The device of claim 1 , wherein:
the critical signal net refers to a first critical signal net,
at least one frontside supply rail of the frontside supply rails is used as a frontside signal path for a second critical signal net that is complementary to the first critical signal net, and the second critical signal net refers to an inverted global timing signal (NGTP).
9. The device of claim 1 , wherein:
the cell architecture includes a flexible bitline (FBL) that is used as the at least one buried supply rail of the buried supply rails, and
the flexible bitline (FBL) is used as the backside signal path for providing the critical signal net to the logic circuitry.
10. The device of claim 9 , further comprising:
buried transition vias that transition the flexible bitline (FBL) between the backside power network and frontside metals.
11. The device of claim 1 , wherein:
the cell architecture includes a global wordline (GWL) that is used as the at least one buried supply rail of the buried supply rails, and
the global wordline (GWL) is used as the backside signal path for providing the critical signal net to the logic circuitry.
12. The device of claim 11 , further comprising:
buried transition vias that transition the global wordline (GWL) between the backside power network and the frontside metals.
13. The device of claim 1 , wherein:
the frontside power network has frontside metal layers that are configurable to provide a core voltage (VDD) or ground (VSS), and
the backside power network has buried metal layers that are configurable to provide the backside signal path for the critical signal net and provide a core voltage (VDD) or ground (VSS).
14. A cell architecture, comprising:
frontside supply rails coupled to logic circuitry;
backside supply rails; and
buried transition vias that couple at least one backside supply rail to the logic circuitry to thereby provide a critical signal net to the logic circuitry.
15. The cell architecture of claim 14 , wherein:
the frontside supply rails are formed with frontside metal,
the backside supply rails are formed with backside buried metal,
the buried transition vias are configured to couple the at least one buried supply rail to the frontside metal to thereby provide the critical signal net to the logic circuitry.
16. The cell architecture of claim 14 , wherein:
the cell architecture includes a flexible bitline (FBL) that is used as the at least one buried supply rail of the buried supply rails, and
the flexible bitline (FBL) is used as the backside signal path for providing the critical signal net to the logic circuitry.
17. The cell architecture of claim 16 , wherein:
the buried transition vias are used to transition the flexible bitline (FBL) between the backside power network and the frontside metals.
18. The cell architecture of claim 14 , wherein:
the cell architecture includes a global wordline (GWL) that is used as the at least one buried supply rail of the buried supply rails, and
the global wordline (GWL) is used as the backside signal path for providing the critical signal net to the logic circuitry.
19. The cell architecture of claim 18 , wherein:
the buried transition vias are used to transition the global wordline (GWL) between the backside power network and the frontside metals.
20. A method, comprising:
providing a frontside power network with frontside power rails coupled to logic;
providing backside power network having buried supply rails; and
providing buried transition vias that couple at least one backside supply rail to the logic so as to thereby provide a critical signal net to the logic,
wherein the at least one buried supply rail provides a backside signal path for providing the critical signal net to the logic.