Hybrid output multiplexer for a high framerate CMOS imager
An imaging system is provided that includes a pixel array having a plurality of columns with rows of pixels and with each pixel having a plurality of photodiodes and a common readout circuit that stores respective accumulation voltages from each of the plurality of photodiodes. Moreover, the system includes row driver circuitry that control the pixel array for pixel addressing and readout, such that the respective accumulation voltages of the photodiodes is read out on a readout channel coupled to a bit line column, and a hybrid multiplexer that multiplexes and routes output signals from the pixel array to a video imaging device to be displayed thereon.
1. A hybrid multiplexer for routing image signals to a video imaging device for display thereon, the hybrid multiplexer comprising:
a first stage including a plurality of tristate multiplexers configured to receive a plurality of digital signals corresponding to image data generated by an image sensor;
a second stage including a plurality of registers configured to receive digital output signals from the first stage and store respective values therein; and
a third stage including at least one digital multiplexer communicatively coupled to the plurality of registers and configured to serially route the digital output signals from the second stage to a control unit for producing a digital image from the image data on the video imaging device,
wherein the second stage is configured to store the received digital output signals to provide a settling time for the first stage to receive subsequent values of the plurality of digital signals that correspond to the image data.
2. The hybrid multiplexer according to claim 1 , wherein the plurality of tristate multiplexers of the first stage includes 11:1 tristate multiplexers, and the digital multiplexer of the third stage comprises a 6:1 digital multiplexer.
3. The hybrid multiplexer according to claim 1 , wherein the plurality of digital signals received by the first stage are analog-to-digital converted signals of accumulation voltages generated by a plurality of photodiodes in a pixel array of the image sensor.
4. The hybrid multiplexer according to claim 1 , wherein the third stage is configured to daisy chain the respective digital output values of the first and second stages to multiplex the plurality of digital output signals to the control unit.
5. The hybrid multiplexer according to claim 4 , wherein the third stage is configured to propagate the respective digital output values to a plurality of digital low-voltage differential signaling (LVDS) output channels.
6. The hybrid multiplexer according to claim 1 , further comprising:
two identical multiplexing operation blocks that each separately include the first stage, the second stage and the third stage; and
a register configured to latch the digital output signals that are output to each of the third stages, respectively.
7. A hybrid multiplexer for routing image signals to a video imaging device for display thereon, the hybrid multiplexer comprising:
a first stage including a plurality of multiplexers configured to receive a plurality of digital signals corresponding to image data generated by an image sensor;
a second stage including a plurality of registers configured to store digital output signals that are output from the first stage, wherein the second stage is configured to store the received digital output signals to provide a settling time for the first stage to receive subsequent values of the plurality of digital signals that correspond to the image data; and
a third stage including at least one digital multiplexer communicatively coupled to the plurality of registers and configured to serially route the digital output signals from the second stage to a control unit for producing a digital image from the image data on the video imaging device.
8. The hybrid multiplexer according to claim 7 , wherein the plurality of digital signals received by the first stage are analog-to-digital converted signals of accumulation voltages generated by a plurality of photodiodes in a pixel array of the image sensor.
9. The hybrid multiplexer according to claim 7 , wherein the third stage is configured to daisy chain the respective digital output values of the first and second stages to multiplex the plurality of digital output signals to the control unit.
10. The hybrid multiplexer according to claim 9 , wherein the third stage is configured to propagate the respective digital output values to a plurality of digital low-voltage differential signaling (LVDS) output channels.
11. The hybrid multiplexer according to claim 7 , further comprising two identical multiplexing operation blocks that each separately include the first stage, the second stage and the third stage.
12. The hybrid multiplexer according to claim 11 , further comprising a register configured to latch the digital output signals that are output to each of the third stages, respectively.
13. The hybrid multiplexer according to claim 7 , wherein the plurality multiplexers of the first stage includes a plurality of 11:1 tristate multiplexers, and the at least one digital multiplexer of the third stage comprises a 6:1 digital multiplexer.
14. A hybrid multiplexer for routing image signals to a video imaging device for display thereon, the hybrid multiplexer comprising:
a first stage including a plurality of multiplexers configured to receive a plurality of digital signals corresponding to image data generated by an image sensor;
a second stage including a plurality of registers configured to store digital output signals that are output from the first stage; and
a third stage including at least one digital multiplexer communicatively coupled to the plurality of registers and configured to serially route the digital output signals from the second stage to a control unit for producing a digital image from the image data on the video imaging device.
15. The hybrid multiplexer according to claim 14 , wherein the plurality of digital signals received by the first stage are analog-to-digital converted signals of accumulation voltages generated by a plurality of photodiodes in a pixel array of the image sensor.
16. The hybrid multiplexer according to claim 14 , wherein the third stage is configured to daisy chain the respective digital output values of the first and second stages to multiplex the plurality of digital output signals to the control unit.
17. The hybrid multiplexer according to claim 16 , wherein the third stage is configured to propagate the respective digital output values to a plurality of digital low-voltage differential signaling (LVDS) output channels.
18. The hybrid multiplexer according to claim 14 , further comprising:
two identical multiplexing operation blocks that each separately include the first stage, the second stage and the third stage; and
at least one register configured to latch the digital output signals that are output to each of the third stages, respectively.
19. The hybrid multiplexer according to claim 14 , wherein the second stage is configured to store the received digital output signals to provide a settling time for the first stage to receive subsequent values of the plurality of digital signals that correspond to the image data.
20. The hybrid multiplexer according to claim 19 , wherein the plurality multiplexers of the first stage includes a plurality of 11:1 tristate multiplexers, and the at least one digital multiplexer of the third stage comprises a 6:1 digital multiplexer.