Droop detection and mitigation
In an embodiment, a method includes filtering, with a low-pass filter, a voltage signal (V dd ) of a chip to create a filtered signal (V ref ). The method further includes dividing V ref by a given factor. The method further includes determining whether a voltage droop occurred in V dd by comparing V dd to the divided V ref . The method further includes outputting a droop detection signal if V dd is less than the divided V ref . In an embodiment, dividing V ref by the given factor includes selecting, with a multiplexer, one of a plurality of divided V ref signals outputted by a voltage divider. The selecting is based on a selection signal.
1. A method comprising:
filtering, with a low-pass filter, a first voltage signal (V dd-1 ) of a root clock of a chip and a second voltage signal (V dd-2 ) of a local clock of the chip to produce a first filtered signal (V ref-1 ) of the root clock and a second filtered signal (V ref-2 ) of the local clock;
dividing V ref-1 and V ref-2 by a given factor;
comparing V dd-1 to the divided V ref-1 and V dd-2 to the divided V ref-2 ; and
outputting a droop detection signal if V dd-1 is less than the divided V ref-1 or if V dd-2 is less than the divided V ref-2 .
2. The method of claim 1 , wherein dividing V ref-1 and V ref-2 by the given factor includes selecting, with a multiplexer, one of a plurality of divided V ref-1 and V ref-2 signals outputted by a voltage divider, the selecting based on a selection signal.
3. The method of claim 1 , wherein outputting the droop detection signal includes setting at least one SR Latch, wherein the SR Latch stores the droop detection signal.
4. The method of claim 3 , wherein the at least one SR Latch includes a local SR Latch and a global SR Latch, wherein the local SR Latch is cleared by a finite state machine local to the local SR latch and the global SR Latch is cleared by a finite state machine global to the chip.
5. The method of claim 1 , further comprising:
upon receiving the droop detection signal, decreasing a frequency of the chip from a full frequency to a lower frequency.
6. The method of claim 5 , further comprising:
increasing the frequency of the chip to at least one intermediate frequency, the intermediate frequency being between the full frequency and the lower frequency.
7. The method of claim 1 , wherein comparing V dd-1 to the divided V ref-1 and V dd-2 to the divided V ref-2 uses a sense amplifier.
8. The method of claim 1 , further comprising:
storing, in a database, the droop detection signal.
9. A droop detection circuit comprising:
a low-pass filter configured to filter a first voltage signal (V dd-1 ) of a root clock of a chip and a second voltage signal (V dd-2 ) of a local clock of the chip to produce a first filtered signal (V ref-1 ) of the root clock and a second filtered signal (V ref-2 ) of the local clock;
a voltage divider configured to divide V ref-1 and V ref-2 by a given factor;
a sense amplifier configured to compare V dd-1 to the divided V ref-1 and V dd-2 to the divided V ref-2 and configured to output a droop detection signal if V dd-1 is less than the divided V ref-1 or if V dd-2 is less than the divided V ref-2 .
10. The droop detection circuit of claim 9 , further comprising:
a multiplexer configured to select one of a plurality of divided V ref-1 and V ref-2 signals outputted by the voltage divider, the selecting being based on a selection signal.
11. The droop detection circuit of claim 9 , further comprising at least one SR Latch, wherein the SR Latch stores the droop detection signal.
12. The droop detection circuit of claim 11 , wherein the at least one SR Latch includes a local SR Latch and a global SR Latch, wherein the local SR Latch is cleared by a finite state machine local to the local SR latch and the global SR Latch is cleared by a finite state machine global to the chip.
13. The droop detection circuit of claim 9 , further comprising:
a clock division module configured to, upon receiving the droop detection signal, decrease a frequency of the chip from a full frequency to a lower frequency.
14. The system of claim 13 , wherein the clock division module is further configured to:
increase the frequency of the chip to at least one intermediate frequency, the intermediate frequency being between the full frequency and the lower frequency.
15. The system of claim 9 , further comprising:
an interface to a database that is configured to store, in a database, the droop detection signal.
16. A processor comprising:
a root clock;
at least one local clock;
a first droop detection circuit located coupled to the root clock configured to detect a global voltage droop in a source voltage;
a second droop detection circuit located coupled to the local clock configured to detect a local voltage droop in the source voltage;
a droop mitigation circuit configured to, in response to the first or second droop detection circuit detecting the voltage droop at the root clock or local clock, respectively, reduce a frequency of the root clock of the processor.
17. The processor of claim 16 , further comprising:
at least one local droop detection circuit being located on a die of the processor.
18. The processor of claim 16 , wherein the first and second droop detection circuits each further include:
a low-pass filter configured to filter a voltage signal (V dd ) of a chip to create a filtered signal (V ref );
a voltage divider configured to divide V ref by a given factor;
a sense amplifier configured to compare V dd to the divided V ref and configured to output a droop detection signal if V dd is less than the divided V ref .
19. The processor of claim 18 , wherein the droop detection circuit further includes:
a multiplexer configured to select one of a plurality of divided V ref signals outputted by the voltage divider, the selecting based on a selection signal.