Configurable function approximation based on switching mapping table content

1. An integrated circuit comprising:

a hardware mapping table comprising a plurality of buckets, each bucket of the plurality of buckets configured to store a base value, wherein each bucket is further configured to, in a first mode of operation, store a first set of function parameters for a value of a function evaluated at the base value, and in a second mode of operation, store a second set of function parameters for the value of the function evaluated at the base value, the second set of function parameters being a subset of and not equal to the first set of function parameters;

a selection module configured to:

receive a request to evaluate the function at an input value; and

select a bucket from the plurality of buckets based on a relationship between the input value and the base value stored in the bucket;

an arithmetic circuit configured to:

determine a difference between the input value and the base value;

receive a control signal that indicates the first mode of operation or the second mode of operation;

determine whether the control signal indicates the first mode of operation or the second mode of operation;

if the control signal indicates the first mode of operation:

obtain the first set of function parameters from the selected bucket; and

determine a first estimated output value of the function at the input value based on the difference and the first set of function parameters;

if the control signal indicates the second mode of operation:

obtain the second set of function parameters from the selected bucket;

determine a second estimated output value of the function at the input value based on the difference and the second set of function parameters; and

quantize the second estimated output value to generate a quantized second estimated output value; and

output the first estimated output value or the quantized second estimated output value.

2. The integrated circuit of claim 1 , wherein:

the first set of function parameters includes a first parameter, a second parameter, a third parameter, and fourth parameter;

the second set of function parameters includes the second parameter, the third parameter, and the fourth parameter;

the arithmetic circuits include a first arithmetic unit, a second arithmetic unit, and a third arithmetic unit each including a multiplier and an adder;

in the first mode of operation:

the first arithmetic unit is configured to process the first parameter, the second parameter, and the difference to generate a first intermediate output;

the second arithmetic unit is configured to process the first intermediate output, the third parameter, and the difference to generate a second intermediate output; and

the third arithmetic unit is configured to process the second intermediate output, the fourth parameter, and the difference to generate the first estimated output value; and

in the second mode of operation:

the first arithmetic unit is configured to process the second parameter, the third parameter, and the difference to generate a third intermediate output;

the second arithmetic unit is configured to process the third intermediate output, the fourth parameter, and the difference to generate the second estimated output value; and

the third arithmetic unit is configured to quantize the second estimated output value to generate the quantized second estimated output value.

3. The integrated circuit of claim 1 , wherein the first set of function parameters includes coefficients of a third-degree Taylor series expansion of the function, and wherein the second set of function parameters includes coefficients of a second-degree Taylor series expansion of the function.

4. The integrated circuit of claim 1 , wherein the hardware mapping table is programmed by an application to store the first set of function parameters in the first mode of operation and to store the second set of function parameters in the second mode of operation.

5. A system comprising:

a controller;

configurable arithmetic circuits; and

a mapping table that stores a first set of function parameters in a first mode of operation and stores a second set of function parameters in a second mode of operation, the second set of function parameters being a subset of and not equal to the first set of function parameters;

wherein the controller:

sends a control signal that indicates the first mode of operation or the second mode of operation;

if the control signal indicates the first mode of operation, configures the arithmetic circuits to:

compute a first approximation result of a function at an input value based on the first set of function parameters; and

output the first approximation result;

if the control signal indicates the second mode of operation, configures the arithmetic circuits to:

compute a second approximation result of the function at the input value based on the second set of function parameters;

perform post-processing of the second approximation result to generate post-processed second approximation result; and

output the post-processed second approximation result.

6. The system of claim 5 , wherein the post-processing of the second approximation result comprises: scaling the second approximation result or quantizing the second approximation result.

7. The system of claim 6 , wherein the first set of function parameters and the second set of function parameters are associated with a base value; and

wherein the arithmetic circuits are configured to:

in the first mode of operation, extrapolate the first set of function parameters from the base value to the input value to compute the first approximation result; and

in the second mode of operation, extrapolate the second set of function parameters from the base value to the input value to compute the second approximation result.

8. The system of claim 5 , wherein:

the arithmetic circuits comprise a subtractor, a first adder, a first multiplier, a second adder, and a second multiplier; and

the subtractor is configured to determine a difference between the base value and the input value.

9. The system of claim 8 , wherein:

the first set of function parameters includes a first function parameter, a second function parameter, and a third function parameter;

in the first mode of operation:

the first multiplier is configured to multiply the difference with the first function parameter to generate a first multiple;

the first adder is configured to add the first multiple with the second function parameter to generate a first intermediate output;

the second multiplier is configured to multiply the difference with the first intermediate output to generate a second multiple; and

the second adder is configured to add the second multiple with the third function parameter to generate the first approximation result.

10. The system of claim 9 , wherein:

the second set of function parameters includes the second function parameter and the third function parameter;

in the second mode of operation:

the first multiplier is configured to multiply the difference with the second function parameter to generate a third multiple;

the first adder is configured to add the third multiple with the third function parameter to generate the second approximation result;

the second multiplier is configured to multiply the second approximation result with a scaling factor to generate a fourth multiple; and

the second adder is configured to add the fourth multiple with an offset to generate the post-processed second approximation result.

11. The system of claim 10 , wherein the scaling factor is a quantization scale factor, and wherein the offset is related to the quantization scale factor.

12. The system of claim 11 , wherein the offset is configured such that the arithmetic circuits generate a zero post-processed second approximation result based on a zero input value.

13. The system of claim 9 , wherein:

the first function parameter is based on evaluating a second derivative of the function at the base value;

the second function parameter is based on evaluating a first derivative of the function at the base value; and

the third function parameter is based on evaluating the function at the base value.

14. The system of claim 5 , wherein:

the arithmetic circuits comprise a subtractor, a first adder, a first multiplier, a second adder, a second multiplier, a third adder, and a third multiplier; and

the subtractor is configured to determine a difference between the base value and the input value.

15. The system of claim 14 , wherein:

the first set of function parameters includes a first function parameter, a second function parameter, a third function parameter, and a fourth function parameter;

the second set of function parameters includes the second function parameter, the third function parameter, and the fourth function parameter;

in the first mode of operation:

the first multiplier is configured to multiply the difference with the first function parameter to generate a first multiple;

the first adder is configured to add the first multiple with the second function parameter to generate a first intermediate output;

the second multiplier is configured to multiply the difference with the first intermediate output to generate a second multiple;

the second adder is configured to add the second multiple with the third function parameter to generate a second intermediate output;

the third multiplier is configured to multiply the difference with the second intermediate output to generate a third multiple; and

the third adder is configured to add the third multiple with the fourth function parameter to generate the first approximation result;

in the second mode of operation:

the first multiplier is configured to multiply the difference with the second function parameter to generate a fourth multiple;

the first adder is configured to add the fourth multiple with the third function parameter to generate a third intermediate output;

the second multiplier is configured to multiply the difference with the third intermediate output to generate a fifth multiple;

the second adder is configured to add the fifth multiple with the fourth function parameter to generate the second approximation result;

the third multiplier is configured to multiply the second approximation result with a scaling factor to generate a sixth multiple; and

the third adder is configured to add the sixth multiple with an offset to generate the post-processed second approximation result.

16. The system of claim 5 , further comprising:

a computing engine configured to perform arithmetic operations for a neural network layer to generate partial weighted sums;

a summation buffer to generate a set of weighted sums by summing the partial weighted sums; and

wherein the arithmetic circuits are configured to,

in the first mode of operation:

generate a set of first approximation results of applying an activation function to the set of weighted sums; and

store the set of first approximation results at the summation buffer;

in the second mode of operation:

generate a set of quantized second approximation results of applying the activation function to the set of weighted sums to generate the second approximation result;

quantize the second approximation result to generate a set of quantized second approximation results; and

store the set of quantized second approximation results at the summation buffer.

17. The system of claim 16 , further comprising:

a state buffer; and

a pooling engine configured to:

in the first mode of operation:

receive the set of first approximation results from the summation buffer;

perform a first pooling operation on the set of first approximation results to generate a first set of pooling results;

quantize the first set of pooling results to generate a set of quantized pooling results; and

store the first set of quantized pooling results at the state buffer as inputs for arithmetic operations of a next neural network layer; and

in the second mode of operation:

receive the set of quantized second approximation results from the summation buffer; and

store, at the state buffer the set of quantized second approximation results, or a second set of quantized pooling results based on performing a second pooling operation on the set of quantized second approximation results, as inputs for arithmetic operations of a next neural network layer.

18. A method comprising:

receiving an input value;

selecting, based on the input value, a bucket of a mapping table that stores a first set of function parameters under a first mode of operation and a second set of function parameters under a second mode of operation, both the first set of function parameters and the second set of function parameters being associated with a base value, the second set of function parameters being a subset of and not equal to the first set of function parameters;

receiving a control signal that indicates either the first mode of operation or the second mode of operation;

if the control signal indicates the first mode of operation, performing a first operation by:

obtaining the first set of function parameters from the bucket;

extrapolating the first set of function parameters from the base value to the input value to compute a first approximation result; and

outputting the first approximation result; and

if the control signal indicates the second mode of operation, performing a second operation by:

obtaining the second set of function parameters from the bucket;

extrapolating the second set of function parameters from the base value to the input value to compute a second approximation result;

quantizing the second approximation result to generate a quantized second approximation result; and

outputting the quantized second approximation result.

19. The method of claim 18 , further comprising:

storing the first set of function parameters in the bucket in the first mode of operation; and

storing the second set of function parameters in the bucket in the second mode of operation.