Time-to-digital converter calibration
A digital phase-locked loop (DPLL) may include a time-to-digital converter (TDC) to provide a phase error signal, a frequency-divider to perform frequency division on an output signal to generate a frequency-divided output signal, a delta-sigma-modulator (DSM) to provide a test signal that represents a quantization error of the DSM, and a digital-to-time converter (DTC) to at least partially remove the quantization error from the frequency-divided output signal based on the test signal to generate the feedback signal. The DPLL may include a circuit to cause the DTC to provide a percentage of the quantization error such that the percentage of the quantization error is in the phase error signal, and a TDC calibration component to calibrate the TDC by applying a gain adjustment factor to the TDC. The gain adjustment factor may be based on the test signal and the phase error signal including the percentage of the quantization error.
1. A digital phase-locked loop (DPLL), comprising:
a time-to-digital converter (TDC) configured to provide a phase error signal that indicates a phase difference between a reference signal and a feedback signal;
a frequency divider configured to perform frequency division on an output signal of the DPLL to generate a frequency-divided output signal, and
a delta-sigma modulator (DSM) configured to provide a test signal that represents a quantization error of the DSM;
a digital-to-time converter (DTC) configured to at least partially remove the quantization error of the DSM from the frequency-divided output signal based on the test signal to generate the feedback signal;
a circuit component to, during operation in a TDC calibration mode, cause the DTC to provide a predetermined percentage of the quantization error such that the predetermined percentage of the quantization error is included in the phase error signal; and
a TDC calibration component configured to, during operation in the TDC calibration mode, calibrate the TDC by applying a gain adjustment factor to the TDC,
wherein the gain adjustment factor is based on the test signal and the phase error signal including the predetermined percentage of the quantization error.
2. The DPLL of claim 1 , wherein the circuit component is configured to cease causing the predetermined percentage of the quantization error to be included in the phase error signal during operation in a normal operation mode.
3. The DPLL of claim 1 , wherein the predetermined percentage of the quantization error is in a range from approximately 10% of the quantization error to approximately 35% of the quantization error.
4. The DPLL of claim 1 , wherein the predetermined percentage of the quantization error is based on a linear range of the TDC in which gain of the TDC is to be controlled.
5. The DPLL of claim 1 , wherein the TDC calibration component is further configured to:
apply a gain to the test signal to generate a gain adjusted test signal,
wherein the gain applied to the test signal is based on a period of a digitally-controlled oscillator (DCO), an ideal gain of the TDC, and the predetermined percentage of the quantization error included in the phase error signal;
generate a difference signal by determining a difference between the phase error signal and the gain adjusted test signal; and
compute the gain adjustment factor based on the difference signal.
6. The DPLL of claim 1 , wherein the TDC calibration component is configured to compute the gain adjustment factor using a least mean squares (LMS) algorithm.
7. The DPLL of claim 1 , wherein the TDC calibration component, when applying the gain adjustment factor to the TDC to calibrate the TDC, causes a difference between the phase error signal and a gain adjusted test signal to be reduced.
8. The DPLL of claim 1 , wherein the gain adjustment factor corresponds to a result of dividing an ideal gain of the TDC by an actual gain of the TDC.
9. The DPLL of claim 1 , wherein the TDC calibration component is configured to freeze the gain adjustment factor during operation in a normal operation mode.
10. The DPLL of claim 1 , wherein the TDC calibration component is configured to calibrate the TDC while the DPLL is operating in a phase-locked state.
11. A digital phase-locked loop (DPLL), comprising:
a time-to-digital converter (TDC) configured to provide a phase error signal that indicates a phase difference between a reference signal and a feedback signal;
a frequency divider configured to perform frequency division on an output signal of the DPLL to generate the feedback signal;
a delta-sigma modulator (DSM) configured to provide a test signal associated with calibrating the TDC, wherein the test signal represents a quantization error of the DSM; and
a TDC calibration component configured to calibrate the TDC while the DPLL is operating in a phase-locked state by applying a gain adjustment factor to the TDC, wherein the gain adjustment factor is based on the phase error signal and the test signal.
12. The DPLL of claim 11 , wherein the TDC calibration component is further configured to:
apply a gain to the test signal to generate a gain adjusted test signal,
wherein the gain applied to the test signal is based on a period of a digitally-controlled oscillator (DCO) and an ideal gain of the TDC;
generate a difference signal by determining a difference between the phase error signal and the gain adjusted test signal; and
compute the gain adjustment factor based on the difference signal.
13. The DPLL of claim 11 , wherein the TDC calibration component is configured to compute the gain adjustment factor using a least mean squares (LMS) algorithm.
14. The DPLL of claim 11 , wherein the TDC calibration component, when applying the gain adjustment factor to the TDC to calibrate the TDC, causes a difference between the phase error signal and a gain adjusted test signal to be reduced.
15. The DPLL of claim 11 , wherein the gain adjustment factor corresponds to a result of dividing an ideal gain of the TDC by an actual gain of the TDC.
16. A method, comprising;
causing, during operation in a time-to-digital converter (TDC) calibration mode, a predetermined percentage of a quantization error of a delta-sigma modulator (DSM) of a digital phase-locked loop (DPLL) to be included in a phase error signal provided by a TDC of the DPLL;
calibrating, during operation in the TDC calibration mode, the TDC by applying a gain adjustment factor to the TDC,
wherein the gain adjustment factor is based on a test signal representing the quantization error of the DSM and the phase error signal including the predetermined percentage of the quantization error;
determining that a gain of the TDC matches an ideal gain of the TDC;
freezing the gain of the TDC and entering a normal operation mode based on determining that the gain of the TDC matches the ideal gain of the TDC; and
preventing, during operation in the normal operation mode, the quantization error from being included in the phase error signal provided by the TDC.
17. The method of claim 16 , wherein causing the predetermined percentage of the quantization error to be included in the phase error signal comprises forcing a particular percentage of a gain of a digital-to-time converter (DTC).
18. The method of claim 16 , wherein preventing the quantization error from being included in the phase error signal comprises restoring 100% of a gain of a digital-to-time converter (DTC).
19. The method of claim 16 , further comprising:
determining that the DPLL has reached a phase-locked state, and
entering the TDC calibration mode based on determining that the DPLL has reached the phase-locked state.
20. The method of claim 16 , further comprising re-entering operation in the TDC calibration mode based on determining that a temperature condition associated with the DPLL is satisfied.