Writing scheme for multi-element gain ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches and control on the plate-lines of the bit-cell
A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.
1. An apparatus comprising:
a first node;
a second node;
a first capacitor comprising non-linear polar material, the first capacitor having a first terminal coupled to the first node;
a second capacitor comprising the non-linear polar material, the second capacitor having a first terminal coupled to the first node;
a first transistor coupled to the first node and a bit-line, wherein the first transistor is controllable by a word-line;
a second transistor having a gate terminal coupled to the first node, and a source terminal coupled to a sense-line and a drain terminal coupled to the second node;
a first switch coupled to the first capacitor and a first plate-line, the first switch controllable by a first control;
a second switch coupled to the second capacitor and a second plate-line, the second switch controllable by a second control; and
one or more circuitries to boost the word-line above a voltage supply level during a write operation, wherein the one or more circuitries is to cause a voltage drop across one of the first capacitor or the second capacitor, between two different write operations, to be the voltage supply level or a negative voltage supply level.
2. The apparatus of claim 1 , wherein the write operation includes a first write operation and a second write operation, wherein the one or more circuitries is to generate a first pulse on the bit-line for a first write operation, and wherein the first pulse has an amplitude of the voltage supply level.
3. The apparatus of claim 2 , wherein the one or more circuitries is to apply a 0V on the bit-line for the second write operation different from the first write operation.
4. The apparatus of claim 3 , wherein the one or more circuitries is to apply a second pulse on the first plate-line for the second write operation, and wherein the second pulse has an amplitude of the voltage supply level.
5. The apparatus of claim 3 , wherein the one or more circuitries is to apply a 0V on the first plate-line for the first write operation.
6. The apparatus of claim 4 , wherein the second pulse starts and ends substantially when the first pulse starts and ends.
7. The apparatus of claim 1 , wherein the one or more circuitries is to generate a third pulse on the first control, and wherein the third pulse has a pulse width which is same as a pulse width on the word-line.
8. The apparatus of claim 7 , wherein the one or more circuitries is to apply a 0V on the second control.
9. The apparatus of claim 7 , wherein the third pulse has an amplitude which is substantially equal to the boosted word-line.
10. The apparatus of claim 1 , wherein the one or more circuitries is to boost the word-line by about 0.3V above the voltage supply level.
11. The apparatus of claim 1 , wherein the one or more circuitries is to boost the word-line by about 1.5× of a threshold voltage of the first transistor.
12. The apparatus of claim 1 , wherein:
the first transistor is on a frontend of a die, and wherein the first switch and the second switch are on a backend of the die;
the first capacitor and the second capacitor are planar capacitors or non-planar capacitors;
the second node is biased, put on a high-impedance state, or set to 0V; and
the sense-line is biased, put on a high-impedance state, or set to 0V.
13. The apparatus of claim 1 , wherein the first capacitor and the second capacitor are vertically stacked.
14. The apparatus of claim 1 comprising a refresh circuitry to refresh charges on the first capacitor and the second capacitor.
15. The apparatus of claim 1 , wherein the bit-line is parallel to the first plate-line and the second plate-line.
16. The apparatus of claim 1 , wherein the non-linear polar material is one of: ferroelectric material, paraelectric material, or non-linear dielectric.
17. An apparatus comprising:
a first node;
a second node;
a plurality of capacitors coupled to the first node, wherein an individual capacitor of the plurality of capacitors comprises non-linear polar material;
a first transistor coupled to the first node and a bit-line, wherein the first transistor is controllable by a word-line;
a second transistor having a gate terminal coupled to the first node, and a source terminal coupled to a sense-line and a drain terminal coupled to the second node;
a plurality of switches coupled to the plurality of capacitors, wherein an individual switch is controllable by an individual control;
a plurality of plate-lines coupled to the plurality of switches, wherein an individual plate-line is coupled to the individual switch; and
one or more circuitries to boost the word-line above a voltage supply level during a write operation, wherein the one or more circuitries is to cause a voltage drop across the individual capacitor of the plurality of capacitors, between two different write operations, to be the voltage supply level or a negative voltage supply level, and wherein the one or more circuitries is to control the individual control, the individual plate-line, and the bit-line during the write operation.
18. The apparatus of claim 17 , wherein the plurality of switches is controlled by a plurality of controls, wherein the individual control is boosted above the voltage supply level during the write operation, and wherein the bit-line is parallel to the plurality of plate-lines.
19. The apparatus of claim 17 , wherein:
the second node is biased, put on a high-impedance state, or set to 0V; and
the sense-line is biased, put on a high-impedance state, or set to 0V.
20. A system comprising:
a processor circuitry to execute one or more instructions;
a communication interface to allow the processor circuitry to communicate with another device; and
a memory coupled to the processor circuitry, wherein the memory comprises:
a first node;
a second node;
a first capacitor comprising non-linear polar material, the first capacitor having a first terminal coupled to the first node;
a second capacitor comprising the non-linear polar material, the second capacitor having a first terminal coupled to the first node;
a first transistor coupled to the first node and a bit-line, wherein the first transistor is controllable by a word-line;
a second transistor having a gate terminal coupled to the first node, and a source terminal coupled to a sense-line and a drain terminal coupled to the second node;
a first switch coupled to the first capacitor and a first plate-line, the first switch controllable by a first control;
a second switch coupled to the second capacitor and a second plate-line, the second switch controllable by a second control; and
one or more circuitries to boost the word-line above a voltage supply level during a write operation, wherein the one or more circuitries is to ensure a maximum electrical field across the first capacitor or the second capacitor, between two different write operations.