IP Library › Granted Patent US 12,212,321
Granted Patent B1
US 12,212,321 · App. 18/340,827 · Granted Jan 28, 2025

Non-linear polar material based flip-flop

Inventors: Amrita Mathuriya (Portland, OR); Ikenna Odinaka (Durham, NC); Rajeev Kumar Dokania (Beaverton, OR); Rafael Rios (Austin, TX); Sasikanth Manipatruni (Portland, OR)
Assignee: Kepler Computing Inc.
H03K19/185H01L28/55H03K19/21H03K19/23G11C7/106G11C7/1087
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Quick Facts
Patent No.
US 12,212,321
App. No.
18/340,827
Granted
Jan 28, 2025
Kind
B1
Abstract

A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. In one example, a sequential circuit includes pass-gates and inverters, but without a feedback mechanism or memory element. In another example, a sequential uses load capacitors (e.g., capacitors coupled to a storage node and a reference supply). The load capacitors are implemented using ferroelectric material, paraelectric material, or linear dielectric. In one example, a sequential uses minority, majority, or threshold gates with ferroelectric or paraelectric capacitors. In one example, a sequential circuit uses minority, majority, or threshold gates configured as NAND gates.

Claims (35)

1. An apparatus comprising:

a first latch; and

a second latch coupled to the first latch, wherein the first latch comprises:

a first minority gate having a first input to receive data, a second input to receive a clock, and a third input to receive a reference voltage, wherein the first minority gate is to generate a first output which is a first minority function of the data, the clock, and the reference voltage; and

a second minority gate having a fourth input to receive the first output, a fifth input to receive the first output, a sixth input to receive the clock, a seventh input to receive the reference voltage, and an eighth input, wherein the second minority gate is to generate a second output which is a second minority function of the first output, the first output, the clock, the reference voltage, and an inversion of the second output, wherein the first latch is a supervisor latch, wherein the second latch is a supervisee latch, wherein the clock is a first clock, and wherein the second latch is to receive a second clock which is an inverse of the first clock.

2. The apparatus of claim 1 , wherein the second latch comprises:

a third minority gate to receive the second output, the second clock, and the reference voltage, wherein the third minority gate is to generate a third output which is a third minority function of the second output, the second clock, and the reference voltage, wherein the second clock is an inverse of the first clock.

3. The apparatus of claim 2 , wherein the second latch comprises:

a fourth minority gate to receive the third output, the second clock, the reference voltage, and an inverse of a fourth output, wherein the fourth minority gate is to generate the fourth output which is a fourth minority function of the third output, the third output, the second clock, the reference voltage, and an inversion of the fourth output.

4. The apparatus of claim 3 , wherein the fourth minority gate includes a non-linear polar material.

5. The apparatus of claim 2 , wherein the third minority gate includes a non-linear polar material.

6. The apparatus of claim 2 , wherein the third minority gate is operable as an NAND gate.

7. The apparatus of claim 1 , wherein the reference voltage is ground.

8. The apparatus of claim 1 , wherein the first minority gate includes a non-linear polar material.

9. The apparatus of claim 1 , wherein the second minority gate includes a non-linear polar material.

10. The apparatus of claim 9 , wherein the non-linear polar material includes Mn and Sc dopants.

11. The apparatus of claim 9 , wherein the non-linear polar material includes one of: a ferroelectric material, a paraelectric material, or a non-linear dielectric.

12. The apparatus of claim 1 , wherein the first minority gate is operable as an NAND gate.

13. An apparatus comprising:

one or more circuitries to sample data by a clock based at least in part on at least two 3-input minority gates and at least two 5-input minority gates, wherein a first 5-input minority gate of the at least two 5-input minority gates has an output coupled to an input of a first 3-input minority gate of the at least two 3-input minority gates, wherein the at least two 3-input minority gates and the at least two 5-input minority gates comprise non-linear polar material, and wherein the first 3-input minority gate comprises:

a first capacitor, with the non-linear polar material, having a first terminal to receive the clock and a second terminal coupled to a node;

a second capacitor, with the non-linear polar material, having a first terminal to receive the data and a second terminal coupled to the node; and

a third capacitor, with the non-linear polar material, having a first terminal to receive the output and a second terminal coupled to the node, wherein the node is coupled to one of a 5-input minority gate of the at least two 5-input minority gates.

14. The apparatus of claim 13 , wherein the non-linear polar material includes Mn and Sc dopants.

15. The apparatus of claim 13 , wherein the non-linear polar material includes one of: a ferroelectric material, a paraelectric material, or a non-linear dielectric.

16. A system comprising:

a processor circuitry to execute one or more instructions;

a memory to store the one or more instructions; and

a communication interface communicatively coupled to the processor circuitry, wherein the processor circuitry comprises a flip-flop, which includes:

one or more circuitries to sample data by a clock based at least in part on at least two 3-input minority gates and at least two 5-input minority gates, wherein a first 5-input minority gate of the at least two 5-input minority gates has an output coupled to an input of a first 3-input minority gate of the at least two 3-input minority gates, wherein the at least two 3-input minority gates and the at least two 5-input minority gates comprise non-linear polar material, and wherein the first 3-input minority gate comprises:

a first capacitor, with the non-linear polar material, having a first terminal to receive the clock and a second terminal coupled to a node;

a second capacitor, with the non-linear polar material, having a first terminal to receive the data and a second terminal coupled to the node; and

a third capacitor, with the non-linear polar material, having a first terminal to receive the output and a second terminal coupled to the node, wherein the node is coupled to one of a 5-input minority gate of the at least two 5-input minority gates.

17. The system of claim 16 , wherein the non-linear polar material includes Mn and Sc dopants.

18. The system of claim 16 , wherein the non-linear polar material includes one of: a ferroelectric material, a paraelectric material, or a non-linear dielectric.

Continuity (3)
Continuation 18059938 · Nov 29, 2022
Continuation 17407972 · Aug 20, 2021
Continuation 17407031 · Aug 19, 2021
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