IP Library › Granted Patent US 12,299,307
Granted Patent B2
US 12,299,307 · App. 17/495,810 · Granted May 13, 2025

Systems and methods for data transfer for computational storage devices

Inventors: Oscar P. Pinto (San Jose, CA); Ramdas P. Kachare (Pleasanton, CA)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
G06F3/0644G06F3/0622G06F3/067G06F9/544
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Quick Facts
Patent No.
US 12,299,307
App. No.
17/495,810
Granted
May 13, 2025
Kind
B2
Abstract

Provided are systems, methods, and apparatuses for managing memory. The method can include: establishing a connection via an interface, between a host device and a storage device; and transferring data, via the interface, between first memory associated with the host device and second memory associated with the storage device by performing a data operation on the second memory by an application executed by the host, where the storage device includes a processing element that accelerates the data operation by performing at least one offload function on the data operation.

Claims (42)

1. A method to manage memory, the method comprising:

establishing a connection, via an interface, between a host device and a storage device; and

transferring data, via the interface, from first memory associated with the host device to second memory associated with the storage device,

wherein the interface comprises an application programming interface (API), and the host device allocates the second memory using at least one command associated with the API;

wherein the storage device includes a flash storage and a processing element that accelerates a data operation by performing at least one offload function on the data operation of an application,

wherein the data operation is performed on the data by the storage device,

wherein the data is transferred between the first memory and the second memory based at least in part on the at least one offload function, and

wherein the at least one offload function is based at least in part on the data operation of the application.

2. The method of claim 1 , wherein the host device allocates the second memory using a fine-grained allocation scheme or a coarse-grained allocation scheme.

3. The method of claim 1 , wherein the method further comprises addressing the second memory and the transferring data is based at least in part on the addressing of the second memory.

4. The method of claim 1 , wherein the second memory comprises a secure address space, wherein the method further comprises host device performing one or more multitenant operations based on the secure address space, and wherein the secure address space protects the data of a first tenant from access by a second tenant.

5. The method of claim 1 , wherein the storage device comprises a non-volatile memory express (NVMe) enabled storage device and the data operation is performed using a scatter gather list (SGL).

6. The method of claim 1 , wherein the performing the data operation further comprises the storage device transferring data from persistent memory associated with the storage device to the second memory.

7. The method of claim 1 , wherein the transferring data further comprises the host device providing information regarding the first memory's layout to the storage device.

8. The method of claim 1 , wherein the transferring data further comprises the storage device providing information regarding the storage device's memory layout for read and write operations to the host device.

9. The method of claim 1 , wherein the establishing the connection comprises a discovery and setup process.

10. The method of claim 1 , wherein the offload function accesses a result of the data operation from the second memory associated with the storage device.

11. A non-transitory computer-readable medium storing computer-executable instructions for managing memory which, when executed by a processor, cause the processor to perform operations comprising:

establishing a connection, via an interface, between a host device and a storage device; and

transferring data, via the interface, from first memory associated with the host device to second memory associated with the storage device,

wherein the interface comprises an application programming interface (API), and the host device allocates the second memory using at least one command associated with the API;

wherein the storage device includes a flash storage and a processing element that accelerates a data operation by performing at least one offload function on the data operation of an application,

wherein the data operation is performed on the data by the storage device,

wherein the data is transferred between the first memory and the second memory based at least in part on the at least one offload function, and

wherein the at least one offload function is based at least in part on the data operation of the application.

12. The non-transitory computer-readable medium of claim 11 , wherein the computer-executable instructions further cause the processor to perform operations comprising addressing the second memory, and the transferring data is based at least in part on the addressing of the second memory.

13. The non-transitory computer-readable medium of claim 11 , wherein the second memory comprises a secure address space, wherein the host device performs one or more multitenant operations based on the secure address space and wherein the secure address space protects the data of a first tenant from access by a second tenant.

14. The non-transitory computer-readable medium of claim 11 , wherein the storage device comprises a non-volatile memory express (NVMe) enabled storage device and the data operation is performed using a scatter gather list (SGL).

15. The non-transitory computer-readable medium of claim 11 , wherein the data operation further comprises the storage device transferring data from persistent memory associated with the storage device to the second memory.

16. A system for managing memory, comprising:

a host device comprising a first memory and an application;

a storage device comprising a device manager, a flash storage, a processing element, and a second memory;

wherein the system stores computer-executable instructions which, when executed by a processor, cause the processor to perform operations comprising:

establishing a connection, via an interface, between the host device and the storage device; and

transferring data, via the interface, from first memory associated with the host device to second memory associated with the storage device,

wherein the interface comprises an application programming interface (API), and the host device allocates the second memory using at least one command associated with the API;

wherein the device manager configures the processing element to accelerate a data operation by performing at least one offload function on the data operation of an application,

wherein the data operation is performed on the data by the processing element,

wherein the data is transferred between the first memory and the second memory based at least in part on the at least one offload function, and

wherein the at least one offload function is based at least in part on the data operation of the application.

17. The system of claim 16 , wherein the storage device transfers second data, via the interface, between at least a third memory associated with the storage device and a fourth memory associated with the storage device.

18. The system of claim 16 , wherein the storage device transfers second data, via the interface, between at least a third memory associated with the storage device and a fourth memory associated with the host device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 31, 2023
From: PINTO, OSCAR P.; KACHARE, RAMDAS P.
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 064442/0203 →
Continuity (4)
Provisional Application 63241525 · Sep 7, 2021
Provisional Application 63144469 · Feb 1, 2021
Provisional Application 63142485 · Jan 27, 2021
Related Publication 20220236902A1 · Jul 28, 2022
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