Granted Patent B1

US 12,348,697 · App. 17/929,208 · Granted Jul 1, 2025

Inventors: Andrew Samuel Berkovich (Bellevue, WA); Karina Singer (Seattle, WA); Lyle David Bainbridge (Redwood City, CA); Song Chen (Redmond, WA)

Assignee: Meta Platforms Technologies, LLC

H04N1/4486G06V10/462G06V10/70

Abstract

Claims (33)

1. A privacy control circuit comprising:

an array of pixel cells having a first output data path and a second output data path, the first output data path including a one-time data protection circuitry;

a sensor communication interface communicatively coupled to the first output data path;

an on-sensor processor coupled to the second output data path and communicatively attached to the sensor communication interface; and

a data register communicatively attached to the sensor communication interface.

2. The circuit of claim 1 , further comprising a multiplexer configured for selecting between a raw data input signal over the first output data path and a privacy preserving input signal over the second output data path.

3. The circuit of claim 1 , wherein the on-sensor processor is configured to obfuscate sensitive image data through encryption, feature extraction, information extraction, image filtering, or a combination thereof.

4. The circuit of claim 3 , wherein the feature extraction includes at least one of scale-invariant feature transformation (SIFT), hidden layers, and latent space in machine learning workloads.

5. The circuit of claim 3 , wherein the information extraction includes at least one of object detection, tracking, and classification.

6. The circuit of claim 3 , wherein the image filtering includes sparse sensing.

7. The circuit of claim 1 , wherein the one-time data protection circuitry includes one of a polysilicon fuse, a one-time programmable fuse, a via fuse, high voltage transistors, and polyfuse.

8. The circuit of claim 1 , wherein the first output data path includes a plurality of data paths.

9. The circuit of claim 8 , wherein the one-time data protection circuitry includes a plurality of fuses, each of the fuses coupled to a respective one of the plurality of data paths.

10. The circuit of claim 1 , wherein the one-time data protection circuitry is coupled in series with the first output data path.

11. The circuit of claim 1 , wherein the one-time data protection circuitry is coupled to an input of one or more logic gates or flops.

12. The circuit of claim 1 , wherein the activation of the one-time data protection circuitry disables dataflow over the first output data path while dataflow over the second output data path is uninterrupted, preventing access to unprotected raw image data.

13. The circuit of claim 1 , wherein the sensor communication interface writes to the data register.

14. The circuit of claim 1 , wherein the first output data path is configured to transmit raw image data.

15. The circuit of claim 1 , wherein the second output data path is configured to transmit processed image data.

16. The circuit of claim 1 , wherein data transmission over the one-time data protection circuitry is destroyed in response to an application of a voltage great than to disable communication over the first output data path.

17. A method for protecting raw data from being accessed, the method comprising:

initiating a traditional operating mode for configuring a device;

accessing raw data from an array of pixel cells provided over a first output data path;

completing configuration of the device; and

activating a one-time data protection circuitry connected in series with the first output data path, the activation of the one-time data protection circuitry disabling access to the raw data provided over the first output data path.

18. The method of claim 17 , wherein the one-time data protection circuitry includes one of a polysilicon fuse, a one-time programmable fuse, a via fuse, high voltage transistors, and polyfuse.

19. The method of claim 17 , further comprising a second output data path including processed image data from the array of pixel cells.

20. An artificial reality system, comprising:

an array of pixel cells having a first output data path and a second output data path, the first output data path including a one-time data protection circuitry;

a sensor communication interface communicatively attached to the first output data path;

an on-sensor compute coupled to the second output data path and communicatively attached to the sensor communication interface;

a data register communicatively attached to the sensor communication interface; and

a display for outputting an artificial reality content.

Assignments (1)

References Cited (13)