Oscillator amplitude calibration
Multiple voltage amplitudes for an oscillator in a phase-locked loop may be selected to meet various design goals/criteria (e.g., frequency range of operation, jitter, power consumption, etc.). These multiple voltage amplitudes may be stored in a lookup table memory that relates frequency ranges to reference voltages. A reference voltage for a particular oscillator may then be selected and generated. A feedback loop may compare the amplitude output by the oscillator to the reference voltage and adjusts a bias current of the oscillator with the goal of substantially equalizing the oscillator output to the reference voltage.
1. An integrated circuit, comprising:
an inductor-capacitor (LC) tank oscillator having an output signal and a bias current control input; and
feedback circuitry to, based on a reference voltage indicator received from a lookup table, adjust the bias current control input to minimize a difference between a reference voltage based on the reference voltage indicator and an indicator of the magnitude of the output signal, wherein the reference voltage is generated by a digital-to-analog converter that receives the reference voltage indicator.
2. The integrated circuit of claim 1 , wherein the indicator of the magnitude of the output signal is generated using rectifier circuitry.
3. The integrated circuit of claim 1 , wherein the bias current control input receives a multi-bit digital value.
4. The integrated circuit of claim 3 , wherein the multi-bit digital value is thermometer coded.
5. The integrated circuit of claim 4 , further comprising:
a comparator receiving the reference voltage and the indicator of the magnitude of the output signal, and producing a comparator output signal; and
calibration circuitry to receive the comparator output signal and to, based on the comparator output signal, adjust the multi-bit digital value to minimize the difference between the reference voltage based on the reference voltage indicator and an indicator of the magnitude of the output signal.
6. A method, comprising:
receiving, from a memory on an integrated circuit, a first target amplitude value;
generating a first reference voltage based on the first target amplitude value;
producing a first output amplitude indicator voltage from a first output signal of a first inductor-capacitor (LC) tank oscillator;
adjusting a first current bias of the first LC tank oscillator based on a first comparison of the first reference voltage and the first output amplitude indicator voltage; and
receiving, from the memory on the integrated circuit, a second target amplitude value that is not equal to the first target amplitude value;
generating a second reference voltage based on the second target amplitude value;
producing a second output amplitude indicator voltage from a second output signal of a second inductor-capacitor (LC) tank oscillator; and
adjusting a second current bias of the second LC tank oscillator based on a second comparison of the second reference voltage and the second output amplitude indicator voltage.
7. The method of claim 6 , wherein the first output amplitude indicator voltage is produced by a rectification of the first output signal.
8. The method of claim 7 , wherein the first comparison of the first reference voltage and the first output amplitude indicator voltage is produced by a first comparator and is manifested as a first comparator output signal.
9. The method of claim 8 , wherein the adjusting of the first current bias is done to minimize a difference between the first reference voltage and the first output amplitude indicator voltage.
10. The method of claim 9 , wherein the first current bias is adjusted using a multi-bit digital value.
11. The method of claim 10 , wherein the multi-bit digital value is thermometer encoded.
12. The method of claim 10 , wherein the first LC tank oscillator is part of a first phase-locked loop and the second LC tank oscillator is part of a second phase-locked loop.
13. An integrated circuit, comprising: a memory to provide a first reference voltage indicator; and a first phase-locked loop comprising: an inductor-capacitor (LC) tank oscillator having an output signal and a bias current control input; and feedback circuitry to, based on the first reference voltage indicator received from the memory, adjust a bias current control input signal to minimize a difference between a reference voltage based on the first reference voltage indicator and an indicator of the magnitude of the output signal.
14. The integrated circuit of claim 13 , further comprising:
a second phase-locked loop, the memory to provide the second phase-locked loop with a second reference voltage indicator.
15. The integrated circuit of claim 13 , further comprising:
rectifier circuitry to produce the indicator of the magnitude of the output signal.
16. The integrated circuit of claim 15 , further comprising:
digital-to-analog converter circuitry that receives the reference voltage indicator and produces the reference voltage based on the reference voltage indicator.
17. The integrated circuit of claim 16 , wherein the first reference voltage indicator is selected based on a first performance goal for the first phase-locked loop.
18. The integrated circuit of claim 17 , wherein the second reference voltage indicator is selected based on a second performance goal for the second phase-locked loop.