Processing cache evictions in a directory snoop filter with ECAM
Techniques for maintaining cache coherency while sharing data among multiple processors are disclosed. Multiple coherent elements are arranged in an M×N mesh topology. An element can include a compute coherency block (CCB), and a coherency ordering agent (COA). The COAs include a directory snoop filter (DSF), an eviction content addressable memory (eCAM), a miss and snoop queue (MSQ), and a pipeline logic. The CCB and COA include functions for interfacing with a hierarchical cache and directory snoop filter (DSF). A CCB from within one of the multiple coherent elements issues a read request. The corresponding directory snoop filter (DSF) is inspected to determine if there is a slot (way) available for storing information pertaining to the read request. In the event that no eligible vacancies are present in the DSF, a multi-pass process for handling a capacity limit in a DSF is performed.
1 . A processor-implemented method for sharing data comprising:
accessing a system-on-a-chip (SOC), wherein the SOC includes one or more compute coherency blocks (CCBs) and one or more coherency ordering agents (COAs), wherein a first COA within the one or more COAs comprises a directory snoop filter (DSF), an eviction content addressable memory (eCAM), a miss and snoop queue (MSQ), and a pipeline logic, wherein the DSF comprises N ways;
initiating, by a first CCB in the one or more CCBs, a read request to a first address, wherein the first address includes a first index, wherein the read request misses in the DSF, and wherein the DSF is occupied with a valid data at each way of the N ways corresponding to the first index;
selecting, by the DSF, a cache line for eviction, wherein the cache line includes the first index and a selected way within the N ways, wherein the first index and the selected way are stored in an entry within one or more entries of the eCAM;
saving the read request from the first CCB in the MSQ;
arbitrating, by the eCAM, for the pipeline logic within the COA, wherein the arbitrating includes selecting, by the eCAM, the entry to send to the pipeline logic;
sending, by the eCAM, to the pipeline logic, the entry, wherein the sending causes a cache line associated with the first index to be evicted from the DSF, wherein the cache line is associated with a second address, wherein the sending includes writing, to the eCAM, by the DSF, the second address, wherein the second address overwrites the entry in the eCAM, and wherein the sending includes generating, by the pipeline logic, a snoop of the second address;
mediating, by the MSQ, for the pipeline logic within the COA, wherein the mediating includes replaying, to the pipeline logic, by the MSQ, the read request to the first address; and
starting, by the COA, the read request to the first address, wherein the read request to the first address is handled coherently.
2 . The method of claim 1 wherein the replaying includes searching the DSF for the first address, wherein the searching produces a miss, and wherein the DSF saves information corresponding to the first address at a location, in the DSF, previously occupied by the second address.
3 . The method of claim 1 wherein the selecting is accomplished with a pseudorandom algorithm.
4 . The method of claim 1 further comprising holding another request to the first address from the one or more CCBs, wherein the holding is based on the second address that was written into the eCAM.
5 . The method of claim 4 further comprising saving, to an input FIFO within the COA, the another request to the first address.
6 . The method of claim 5 further comprising awakening the another request, wherein the awakening is based on deleting the second address that was written to the eCAM.
7 . The method of claim 1 further comprising receiving, from the one or more CCBs, one or more responses to the snoop of the second address.
8 . The method of claim 7 further comprising allowing another request, from the one or more CCBs, to the first address, wherein the allowing is based on deleting the entry of the eCAM.
9 . The method of claim 7 further comprising writing back, by the one or more CCBs, a dirty cache line corresponding to the second address.
10 . The method of claim 9 further comprising allowing another request, from the one or more CCBs, to the first address, wherein the allowing is based on deleting the second address that was written to the eCAM.
11 . The method of claim 1 wherein the initiating, the selecting, and the saving comprise a first COA pipeline pass.
12 . The method of claim 11 wherein the arbitrating and the sending comprise a second COA pipeline pass.
13 . The method of claim 12 wherein the mediating and the starting comprise a third COA pipeline pass.
14 . The method of claim 1 wherein the arbitrating includes a third address that was previously stored in the eCAM.
15 . The method of claim 1 wherein the snoop causes an owner of a dirty cache line associated with the second address to perform a writeback to memory.
16 . The method of claim 15 wherein the snoop forces one or more sharers of the second address to back invalidate a shared cache line corresponding to the second address.
17 . The method of claim 1 wherein the DSF includes owner and sharer information for each cache line within a hierarchical cache coupled to the first CCB.
18 . The method of claim 1 wherein the N ways in the DSF are not equal to a number of ways, in a last level cache (LLC) within the first CCB.
19 . The method of claim 1 wherein the SOC includes a network-on-a-chip (NOC), wherein the NOC includes an M×N mesh topology, wherein the M×N mesh topology includes a coherent tile at each point of the M×N mesh topology, and wherein a first coherent tile within the M×N mesh topology includes the first CCB and the first COA.
20 . The method of claim 19 wherein the first COA processes one or more incoming requests received on the M×N mesh topology.
21 . The method of claim 19 wherein the DSF includes owner and sharer information for each cache line within each hierarchical cache coupled to every CCB, within the one or more CCBs, that is coupled to the COA.
22 . A computer system for sharing data comprising:
a memory which stores instructions;
one or more processors coupled to the memory wherein the one or more processors, when executing the instructions which are stored, are configured to:
access a system-on-a-chip (SOC), wherein the SOC includes one or more compute coherency blocks (CCBs) and one or more coherency ordering agents (COAs), wherein a first COA within the one or more COAs comprises a directory snoop filter (DSF), an eviction content addressable memory (eCAM), a miss and snoop queue (MSQ), and a pipeline logic, wherein the DSF comprises N ways;
initiate, by a first CCB in the one or more CCBs, a read request to a first address, wherein the first address includes a first index, wherein the read request misses in the DSF, and wherein the DSF is occupied with a valid data at each way of the N ways corresponding to the first index;
select, by the DSF, a cache line for eviction, wherein the cache line includes the first index and a selected way within the N ways, wherein the first index and the selected way are stored in an entry within one or more entries of the eCAM;
save the read request from the first CCB in the MSQ;
arbitrate, by the eCAM, for the pipeline logic within the COA, wherein the arbitrating includes selecting, by the eCAM, the entry to send to the pipeline logic;
send, by the eCAM, to the pipeline logic, the entry, wherein the sending causes a cache line associated with the first index to be evicted from the DSF, wherein the cache line is associated with a second address, wherein the sending includes writing, to the eCAM, by the DSF, the second address, wherein the second address overwrites the entry in the eCAM, and wherein the sending includes generating, by the pipeline logic, a snoop of the second address;
mediate, by the MSQ, for the pipeline logic within the COA, wherein the mediating includes replaying, to the pipeline logic, by the MSQ, the read request to the first address; and
start, by the COA, the read request to the first address, wherein the read request to the first address is handled coherently.