Granted Patent
Utility
US 4,392,200 · App. 06/239,129
Cached multiprocessor system with pipeline timing
Inventors:
Jega A. Arulpragasam, Robert Giggi, Richard F. Lary, Daniel T. Sullivan
Patented Case
View Patent ↗
Granted: Jul 5, 1983
Filed: Feb 27, 1981
Inventors
Jega A. Arulpragasam
Robert Giggi
Richard F. Lary
Daniel T. Sullivan
Assignee (at issue)
Digital Equipment Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.