IP Library › Granted Patent US 4,468,574
Granted Patent Utility
US 4,468,574 · App. 06/374,586

Dual gate CMOS transistor circuits having reduced electrode capacitance

Inventors: William E. Engeler, Moshe Mazin
Patented Case View Patent ↗
Granted: Aug 28, 1984 Filed: May 3, 1982
Inventors
William E. Engeler
Moshe Mazin
Assignee (at issue)
General Electric Company

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Quick Facts
Patent No.
US 4,468,574
App. No.
06/374,586
Filed
1982-05-03
Granted
1984-08-28
Kind
A