Granted Patent
Utility
US 4,477,962 · App. 06/397,050
Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
Inventor:
Gordon C. Godejahn, Jr.
Patented Case
View Patent ↗
Granted: Oct 23, 1984
Filed: Jul 12, 1982
Inventor
Gordon C. Godejahn, Jr.
Assignee (at issue)
Rockwell International Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.