IP Library › Granted Patent US 4,583,111
Granted Patent Utility
US 4,583,111 · App. 06/530,636

Integrated circuit chip wiring arrangement providing reduced circuit inductance and controlled voltage gradients

Inventor: James M. Early
Patented Case View Patent ↗
Granted: Apr 15, 1986 Filed: Sep 9, 1983
Inventor
James M. Early
Assignee (at issue)
FAIRCHILD SEMICONDUCTOR CORPORATION

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Quick Facts
Patent No.
US 4,583,111
App. No.
06/530,636
Filed
1983-09-09
Granted
1986-04-15
Kind
A