Granted Patent
Utility
US 4,603,471 · App. 06/647,743
Method for making a CMOS circuit having a reduced tendency to latch by controlling the band-gap of source and drain regions
Inventor:
Robert J. Strain
Patented Case
View Patent ↗
Granted: Aug 5, 1986
Filed: Sep 6, 1984
Inventor
Robert J. Strain
Assignee (at issue)
FAIRCHILD SEMICONDUCTOR CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.