IP Library › Granted Patent US 4,612,640
Granted Patent Utility
US 4,612,640 · App. 06/581,685

Error checking and correction circuitry for use with an electrically-programmable and electrically-erasable memory array

Inventors: Sanjay Mehrotra, Gust Perlegos
Patented Case View Patent ↗
Granted: Sep 16, 1986 Filed: Feb 21, 1984
Inventors
Sanjay Mehrotra
Gust Perlegos
Assignee (at issue)
Seeq Technology, Incorporated

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Quick Facts
Patent No.
US 4,612,640
App. No.
06/581,685
Filed
1984-02-21
Granted
1986-09-16
Kind
A