Granted Patent
Utility
US 4,631,425 · App. 06/575,596
Logic gate circuit having P- and N- channel transistors coupled in parallel
Inventor:
Shigeru Koshimaru
Patented Case
View Patent ↗
Granted: Dec 23, 1986
Filed: Jan 31, 1984
Inventor
Shigeru Koshimaru
Assignee (at issue)
NEC CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.