Granted Patent
Utility
US 4,654,780 · App. 06/617,531
Parallel register transfer mechanism for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes
Inventors:
Gary L. Logsdon, Mark R. Scheevel, Brent C. Bolton
Patented Case
View Patent ↗
Granted: Mar 31, 1987
Filed: Jun 5, 1984
Inventors
Gary L. Logsdon
Mark R. Scheevel
Brent C. Bolton
Assignee (at issue)
Burroughs, Inc.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.