IP Library › Granted Patent US 4,740,721
Granted Patent Utility
US 4,740,721 · App. 06/789,383

Programmable logic array with single clock dynamic logic

Inventors: Randall M. Chung, Bradley S. Masters
Patented Case View Patent ↗
Granted: Apr 26, 1988 Filed: Oct 21, 1985
Inventors
Randall M. Chung
Bradley S. Masters
Assignee (at issue)
Western Digital

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Quick Facts
Patent No.
US 4,740,721
App. No.
06/789,383
Filed
1985-10-21
Granted
1988-04-26
Kind
A