Granted Patent
Utility
US 4,751,409 · App. 06/925,306
Coincidence decision circuit composed of MOS OR gate array and MOS AND gate
Inventor:
Jiroh Shimada
Patented Case
View Patent ↗
Granted: Jun 14, 1988
Filed: Oct 31, 1986
Inventor
Jiroh Shimada
Assignee (at issue)
NEC CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.