Granted Patent
Utility
US 4,943,537 · App. 07/372,077
CMOS integrated circuit with reduced susceptibility to PMOS punchthrough
Inventor:
Thomas E. Harrington, III
Patented Case
View Patent ↗
Granted: Jul 24, 1990
Filed: Jun 27, 1989
Inventor
Thomas E. Harrington, III
Assignee (at issue)
Dallas Semiconductor Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.