Granted Patent
Utility
US 4,970,677 · App. 07/361,439
Full adder circuit with improved carry and sum logic gates
Inventor:
William R. Young
Patented Case
View Patent ↗
Granted: Nov 13, 1990
Filed: Jun 5, 1989
Inventor
William R. Young
Assignee (at issue)
HARRIS CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.