Granted Patent
Utility
US 5,118,632 · App. 07/609,801
Dual layer surface gate JFET having enhanced gate-channel breakdown voltage
Inventor:
Gregory A. Schrantz
Patented Case
View Patent ↗
Granted: Jun 2, 1992
Filed: Nov 5, 1990
Inventor
Gregory A. Schrantz
Assignee (at issue)
HARRIS CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.