IP Library › Granted Patent US 5,118,975
Granted Patent Utility
US 5,118,975 · App. 07/489,079

Digital clock buffer circuit providing controllable delay

Inventors: W. Daniel Hillis, Zahi S. Abuhamdeh, Bradley C. Kuszmaul, Jon P. Wade, Shaw-Wen Yang
Patented Case View Patent ↗
Granted: Jun 2, 1992 Filed: Mar 5, 1990
Inventors
W. Daniel Hillis
Zahi S. Abuhamdeh
Bradley C. Kuszmaul
Jon P. Wade
Shaw-Wen Yang
Assignee (at issue)
Thinking Machines, LLC

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Quick Facts
Patent No.
US 5,118,975
App. No.
07/489,079
Filed
1990-03-05
Granted
1992-06-02
Kind
A