IP Library › Granted Patent US 5,155,382
Granted Patent Utility
US 5,155,382 · App. 07/832,742

Two-stage CMOS latch with single-wire clock

Inventors: William C. Madden, Vidya Rajagopalan
Patented Case View Patent ↗
Granted: Oct 13, 1992 Filed: Feb 7, 1992
Inventors
William C. Madden
Vidya Rajagopalan
Assignee (at issue)
Digital Equipment Corporation

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Quick Facts
Patent No.
US 5,155,382
App. No.
07/832,742
Filed
1992-02-07
Granted
1992-10-13
Kind
A