Granted Patent
Utility
US 5,204,543 · App. 07/918,117
Lateral type semiconductor device having a structure for eliminating turning-on of parasitic MOS transistors formed therein
Inventors:
Toshio Hanazawa, Yukinori Fujimura, Takashi Matsumoto
Patented Case
View Patent ↗
Granted: Apr 20, 1993
Filed: Jul 22, 1992
Inventors
Toshio Hanazawa
Yukinori Fujimura
Takashi Matsumoto
Assignees (at issue)
Fujitsu Limited
Fujitsu VSLI Limited
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.