IP Library › Granted Patent US 5,206,821
Granted Patent Utility
US 5,206,821 · App. 07/724,206

Decimation circuit employing multiple memory data shifting section and multiple arithmetic logic unit section

Inventors: William R. Young, William F. Johnstone
Patented Case View Patent ↗
Granted: Apr 27, 1993 Filed: Jul 1, 1991
Inventors
William R. Young
William F. Johnstone
Assignee (at issue)
HARRIS CORPORATION

This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.

Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 5,206,821
App. No.
07/724,206
Filed
1991-07-01
Granted
1993-04-27
Kind
A