Granted Patent
Utility
US 5,208,490 · App. 07/684,720
Functionally complete family of self-timed dynamic logic circuits
Inventor:
Jeffry D. Yetter
Patented Case
View Patent ↗
Granted: May 4, 1993
Filed: Apr 12, 1991
Inventor
Jeffry D. Yetter
Assignee (at issue)
Hewlett-Packard Company, L.P.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.