IP Library › Granted Patent US 5,229,635
Granted Patent Utility
US 5,229,635 · App. 07/748,294

ESD protection circuit and method for power-down application

Inventors: Jeffrey M. Bessolo, Gedaliahoo Krieger
Patented Case View Patent ↗
Granted: Jul 20, 1993 Filed: Aug 21, 1991
Inventors
Jeffrey M. Bessolo
Gedaliahoo Krieger
Assignee (at issue)
VLSI Technology, Inc.

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Quick Facts
Patent No.
US 5,229,635
App. No.
07/748,294
Filed
1991-08-21
Granted
1993-07-20
Kind
A