Granted Patent
Utility
US 5,325,321 · App. 08/087,614
High speed parallel multiplication circuit having a reduced number of gate stages
Inventor:
Ryuji Ishida
Patented Case
View Patent ↗
Granted: Jun 28, 1994
Filed: Jul 2, 1993
Inventor
Ryuji Ishida
Assignee (at issue)
NEC CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.