Apparatus for asserting an end of cycle signal to a processor bus in a computer system if a special cycle is detected on the processor bus without taking action on the special cycle

Granted: Apr 4, 1995 Filed: Mar 22, 1993

This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.