Granted Patent
Utility
US 5,406,590 · App. 07/965,189
Method of and apparatus for correcting edge placement errors in multiplying phase locked loop circuits
Inventors:
Joseph P. Miller, Paul R. Culley
Patented Case
View Patent ↗
Granted: Apr 11, 1995
Filed: Oct 23, 1992
Inventors
Joseph P. Miller
Paul R. Culley
Assignee (at issue)
Compaq Computer Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.