Granted Patent
Utility
US 5,448,705 · App. 08/065,063
RISC microprocessor architecture implementing fast trap and exception state
Inventors:
Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Quang H. Trang
Patented Case
View Patent ↗
Granted: Sep 5, 1995
Filed: May 24, 1993
Inventors
Le Trong Nguyen
Derek J. Lentz
Yoshiyuki Miyayama
Sanjiv Garg
Yasuaki Hagiwara
Johannes Wang
Quang H. Trang
Assignee (at issue)
SEIKO EPSON CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.