IP Library › Granted Patent US 5,457,638
Granted Patent Utility
US 5,457,638 · App. 08/023,828

Timing analysis of VLSI circuits

Inventors: Pranav Ashar, Sharad Malik
Patented Case View Patent ↗
Granted: Oct 10, 1995 Filed: Feb 23, 1993
Inventors
Pranav Ashar
Sharad Malik
Assignees (at issue)
NEC Research Institute, Inc.
The Trustees of Princeton University

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Quick Facts
Patent No.
US 5,457,638
App. No.
08/023,828
Filed
1993-02-23
Granted
1995-10-10
Kind
A