Program counter mechanism having selector for selecting up-to-date instruction prefetch address based upon carry signal of adder which adds instruction size and LSB portion of address register

Granted: Oct 17, 1995 Filed: May 11, 1992

This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.