IP Library › Granted Patent US 5,481,685
Granted Patent Utility
US 5,481,685 · App. 08/345,333

RISC microprocessor architecture implementing fast trap and exception state

Inventors: Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Quang H. Trang
Patented Case View Patent ↗
Granted: Jan 2, 1996 Filed: Nov 21, 1994
Inventors
Le Trong Nguyen
Derek J. Lentz
Yoshiyuki Miyayama
Sanjiv Garg
Yasuaki Hagiwara
Johannes Wang
Quang H. Trang
Assignee (at issue)
SEIKO EPSON CORPORATION

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Quick Facts
Patent No.
US 5,481,685
App. No.
08/345,333
Filed
1994-11-21
Granted
1996-01-02
Kind
A