Granted Patent
Utility
US 5,499,249 · App. 08/251,550
Method and apparatus for test generation and fault simulation for sequential circuits with embedded random access memories (RAMs)
Inventors:
Vishwani D. Agrawal, Tapan Jyoti Chakraborty
Patented Case
View Patent ↗
Granted: Mar 12, 1996
Filed: May 31, 1994
Inventors
Vishwani D. Agrawal
Tapan Jyoti Chakraborty
Assignee (at issue)
AT&T CORP.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.