Granted Patent
Utility
US 5,543,357 · App. 08/351,679
Process of manufacturing a semiconductor device by filling a via hole in an interlayered film of the device with wiring metal
Inventors:
Yoshiaki Yamada, Nobukazu Ito, Kuniko Miyakawa, Michiko Yamanaka
Patented Case
View Patent ↗
Granted: Aug 6, 1996
Filed: Dec 8, 1994
Inventors
Yoshiaki Yamada
Nobukazu Ito
Kuniko Miyakawa
Michiko Yamanaka
Assignee (at issue)
NEC CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.