Granted Patent
Utility
US 5,559,985 · App. 08/115,223
Cache memory having improved hit ratio by selecting the number of bus cycles required for block replacement
Inventor:
Kouji Maemura
Patented Case
View Patent ↗
Granted: Sep 24, 1996
Filed: Sep 1, 1993
Inventor
Kouji Maemura
Assignee (at issue)
NEC CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.