IP Library › Granted Patent US 5,592,102
Granted Patent Utility
US 5,592,102 · App. 08/545,437

Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices

Inventors: Christopher F. Lane, Srinivas T. Reddy, Bonnie I. Wang
Patented Case View Patent ↗
Granted: Jan 7, 1997 Filed: Oct 19, 1995
Inventors
Christopher F. Lane
Srinivas T. Reddy
Bonnie I. Wang
Assignee (at issue)
Altera Corporation

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Quick Facts
Patent No.
US 5,592,102
App. No.
08/545,437
Filed
1995-10-19
Granted
1997-01-07
Kind
A