Granted Patent
Utility
US 5,598,010 · App. 08/648,716
Semiconductor integrated circuit device having dummy pattern effective against micro loading effect
Inventor:
YOSHIHIDE UEMATSU
Patented Case
View Patent ↗
Granted: Jan 28, 1997
Filed: May 16, 1996
Inventor
YOSHIHIDE UEMATSU
Assignee (at issue)
NEC CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.