Granted Patent
Utility
US 5,604,775 · App. 08/536,989
Digital phase locked loop having coarse and fine stepsize variable delay lines
Inventors:
Tetsuo Saitoh, Syuji Matsuo, Itsurou Taniyoshi, Koichi Kitamura
Patented Case
View Patent ↗
Granted: Feb 18, 1997
Filed: Sep 29, 1995
Inventors
Tetsuo Saitoh
Syuji Matsuo
Itsurou Taniyoshi
Koichi Kitamura
Assignee (at issue)
NEC CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.