Granted Patent
Utility
US 5,610,871 · App. 08/341,145
Semiconductor memory device having a hierarchical bit line structure with reduced interference noise
Inventor:
Hideto Hidaka
Patented Case
View Patent ↗
Granted: Mar 11, 1997
Filed: Nov 16, 1994
Inventor
Hideto Hidaka
Assignee (at issue)
MITSUBISHI ELECTRIC CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.