Granted Patent
Utility
US 5,619,418 · App. 08/390,210
Logic gate size optimization process for an integrated circuit whereby circuit speed is improved while circuit area is optimized
Inventors:
David Theodore Blaauw, Joseph W. Norton, Larry G. Jones, Susanta Misra, R. Iris Bahar
Patented Case
View Patent ↗
Granted: Apr 8, 1997
Filed: Feb 16, 1995
Inventors
David Theodore Blaauw
Joseph W. Norton
Larry G. Jones
Susanta Misra
R. Iris Bahar
Assignee (at issue)
Motorola, Inc.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.