Granted Patent
Utility
US 5,636,174 · App. 08/584,565
Fast cycle time-low latency dynamic random access memories and systems and methods using the same
Inventor:
G. R. Mohan Rao
Patented Case
View Patent ↗
Granted: Jun 3, 1997
Filed: Jan 11, 1996
Inventor
G. R. Mohan Rao
Assignee (at issue)
Cirrus Logic Inc.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.