Granted Patent
Utility
US 5,654,652 · App. 08/534,358
High-speed ratio CMOS logic structure with static and dynamic pullups and/or pulldowns using feedback
Inventors:
S. Babar Raza, Hagop Nazarian
Patented Case
View Patent ↗
Granted: Aug 5, 1997
Filed: Sep 27, 1995
Inventors
S. Babar Raza
Hagop Nazarian
Assignee (at issue)
Cypress Semiconductor Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.