Granted Patent
Utility
US 5,665,646 · App. 08/399,361
Method for manufacturing semiconductor device with low electric resistance silicide layer on silicon surface
Inventor:
Tomohisa Kitano
Patented Case
View Patent ↗
Granted: Sep 9, 1997
Filed: Mar 6, 1995
Inventor
Tomohisa Kitano
Assignee (at issue)
NEC CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.